NULL Convention Floating Point Multiplier

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

NULL Convention Floating Point Multiplier

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The ...

متن کامل

Design and Characterization of a Completely Pipelined Null Convention Logic Floating Point Multiplier Anitha

Article history: Received 10 March 2015 Received in revised form 20 March 2015 Accepted 25 March 2015 Available online 10 April 2015

متن کامل

Improved Floating-Point Matrix Multiplier

* This work is partially supported by NSC 99-2221-E-260-010-. † Correspondence to: D.-R. Duh; E-mail address: [email protected] Abstract – Floating-point matrix multiplier is widely used in scientific computations. A great deal of efforts has been made to achieve higher performance. The matrix multiplication consists of many multiplications and accumulations. Yang and Duh proposed a modular des...

متن کامل

A Single Precision Asynchronous Floating Point Multiplier

This paper presents the delay of carry save based multiplier of 65nm technology using Field Programmable Gate Array is in enable mode. Here we present a design of floating point multiplication and that can utilize the decimal carry save addition is reduce path delay and dissipation power. The multiplier can stores a less number of multiplicand uses a decimal carry save addition in the portion o...

متن کامل

A dual precision IEEE floating-point multiplier

We present a design of an IEEE oating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the la-tency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fteen logic levels. A single-precision multiplication can be followed immediately by a...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: The Scientific World Journal

سال: 2015

ISSN: 2356-6140,1537-744X

DOI: 10.1155/2015/749569